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Attacker Value
Unknown
CVE-2021-26369
Disclosure Date: May 10, 2022 (last updated October 07, 2023)
A malicious or compromised UApp or ABL may be used by an attacker to send a malformed system call to the bootloader, resulting in out-of-bounds memory accesses.
0
Attacker Value
Unknown
CVE-2021-26317
Disclosure Date: May 10, 2022 (last updated October 07, 2023)
Failure to verify the protocol in SMM may allow an attacker to control the protocol and modify SPI flash resulting in a potential arbitrary code execution.
0
Attacker Value
Unknown
CVE-2021-26368
Disclosure Date: May 10, 2022 (last updated October 07, 2023)
Insufficient check of the process type in Trusted OS (TOS) may allow an attacker with privileges to enable a lesser privileged process to unmap memory owned by a higher privileged process resulting in a denial of service.
0
Attacker Value
Unknown
CVE-2021-26351
Disclosure Date: May 10, 2022 (last updated October 07, 2023)
Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA (Direct Memory Access) read/write from/to invalid DRAM address that could result in denial of service.
0
Attacker Value
Unknown
CVE-2021-26341
Disclosure Date: March 08, 2022 (last updated October 07, 2023)
Some AMD CPUs may transiently execute beyond unconditional direct branches, which may potentially result in data leakage.
0
Attacker Value
Unknown
CVE-2021-26401
Disclosure Date: March 08, 2022 (last updated October 07, 2023)
LFENCE/JMP (mitigation V2-2) may not sufficiently mitigate CVE-2017-5715 on some AMD CPUs.
0
Attacker Value
Unknown
CVE-2021-26336
Disclosure Date: November 09, 2021 (last updated October 07, 2023)
Insufficient bounds checking in System Management Unit (SMU) may cause invalid memory accesses/updates that could result in SMU hang and subsequent failure to service any further requests from other components.
0
Attacker Value
Unknown
CVE-2021-26337
Disclosure Date: November 09, 2021 (last updated October 07, 2023)
Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests.
0