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Attacker Value
Unknown

CVE-2018-3665

Disclosure Date: June 21, 2018 (last updated November 26, 2024)
System software utilizing Lazy FP state restore technique on systems using Intel Core-based microprocessors may potentially allow a local process to infer data from another process through a speculative execution side channel.
Attacker Value
Unknown

CVE-2018-9056

Disclosure Date: March 27, 2018 (last updated November 26, 2024)
Systems with microprocessors utilizing speculative execution may allow unauthorized disclosure of information to an attacker with local user access via a side-channel attack on the directional branch predictor, as demonstrated by a pattern history table (PHT), aka BranchScope.
0
Attacker Value
Unknown

CVE-2017-5754

Disclosure Date: January 04, 2018 (last updated November 26, 2024)
Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis of the data cache.
0
Attacker Value
Unknown

CVE-2017-5926

Disclosure Date: February 27, 2017 (last updated November 26, 2024)
Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern AMD processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
0
Attacker Value
Unknown

CVE-2017-5925

Disclosure Date: February 27, 2017 (last updated November 26, 2024)
Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern Intel processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
0
Attacker Value
Unknown

CVE-2017-5927

Disclosure Date: February 27, 2017 (last updated November 26, 2024)
Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern ARM processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
0